a processor;

a memory coupled to the processor;

a receptor circuit situated in the IHS;

a frequency synthesizer lock detection system, coupled to the receptor circuit, the frequency synthesizer lock detection system including:

a reference clock that generates a reference clock signal;

a frequency synthesizer including an input coupled to the reference clock and an output at which a synthesizer output signal is generated, the synthesizer output signal being locked in frequency to the reference clock signal;

a distribution network, coupled to the synthesizer output and the receptor circuit, that distributes the synthesizer output signal as a downstream signal to the receptor circuit; and

a lock detector, coupled to the reference clock and the distribution network, that determines if the downstream signal is locked to the reference clock signal,

wherein the lock detector comprises:

a counter apparatus that operates in a first mode to increment a reference clock count by one for each reference clock pulse encountered by the counter apparatus during a first test window exhibiting a predetermined time duration to provide a total count value, the counter apparatus operating in a second mode to decrement the total count value by 1 for every N pulses observed in the downstream signal during a second test window exhibiting the same predetermined time duration as the first test window, thus leaving a final count value in the counter apparatus, the lock detector generating a lock signal to indicate that the downstream signal is locked to the reference clock signal when the final count value is approximately equal to zero.