| US 7,590,137 B1 | ||
| Parameterizable compact network processor for low-level communication with an integrated circuit | ||
| Chi Bun Chan, Longmont, Colo. (US); Jonathan B. Ballagh, Boulder, Colo. (US); and Nabeel Shirazi, San Jose, Calif. (US) | ||
| Assigned to XILINX, Inc., San Jose, Calif. (US) | ||
| Filed on Nov. 22, 2005, as Appl. No. 11/285,708. | ||
| Int. Cl. H04J 3/24 (2006.01) | ||
| U.S. Cl. 370—419 [370/474; 710/20; 703/13] | 7 Claims |
| 1. A network processor disposed on an integrated circuit (IC), said network processor comprising:
an ingress unit comprising a dual port block random access memory;
an egress unit comprising a dual port block random access memory;
a network interface configured to write packetized data to said ingress unit and read packetized data from said egress unit;
and
a coordination processor configured to coordinate movement of data between said ingress unit, said egress unit, and a system
disposed on the IC, said coordination processor further comprising a network processor controller configured to extract non-packetized
data from packetized data stored in said dual port block random access memory of said ingress unit by reading the packetized
data starting at an address immediately following header information of the packetized data, wherein the header information
is discarded, and the coordination processor outputs the non-packetized data without the header information,
wherein said dual port block random access memory of said egress unit comprises read only header information which is inserted
into non-packetized data written to said egress unit to packetize the non-packetized data,
wherein said ingress unit, said egress unit, said network interface, and said coordination processor are disposed within the
IC.
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