| US 7,590,004 B2 | ||
| Nonvolatile semiconductor memory having a plurality of interconnect layers | ||
| Takumi Abe, Yokohama (Japan); Koichi Fukuda, Yokohama (Japan); and Hiroshi Maejima, Chigasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 02, 2006, as Appl. No. 11/345,505. | ||
| Claims priority of application No. 2005-029280 (JP), filed on Feb. 04, 2005; and application No. 2006-011646 (JP), filed on Jan. 19, 2006. | ||
| Prior Publication US 2006/0198196 A1, Sep. 07, 2006 | ||
| Int. Cl. G11C 16/22 (2006.01) | ||
| U.S. Cl. 365—185.18 [365/185.01; 365/185.16; 365/185.17; 257/314; 257/E21.69] | 20 Claims |
| 1. A nonvolatile semiconductor memory comprising:
a memory cell array including horizontally aligned memory cell columns, each of the memory cell columns including vertically
arranged memory cell transistors and select transistors selecting the memory cell transistors;
a plurality of first cell well lines connected to well regions in which the memory cell columns are formed;
a plurality of second cell well lines being arranged in an interconnect layer above the first cell well lines and connected
to the first cell well lines through vias in contact with the first cell well lines and the second cell well lines, so that
the first cell well lines electrically connect to one another; and
a cell source line connected to source terminals of the select transistors in each memory cell column.
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