| US 7,590,000 B2 | ||
| Non-volatile programmable memory cell for programmable logic array | ||
| John McCollum, Saratoga, Calif. (US); Hung-Sheng Chen, San Jose, Calif. (US); and Frank Hawley, Campbell, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Jun. 13, 2007, as Appl. No. 11/762,451. | ||
| Application 11/762451 is a continuation of application No. 11/233396, filed on Sep. 21, 2005, granted, now 7,245,535. | ||
| Prior Publication US 2007/0230244 A1, Oct. 04, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 14/00 (2006.01) | ||
| U.S. Cl. 365—185.08 [365/185.05; 365/185.25] | 37 Claims |
| 1. A non-volatile programmable memory cell comprising:
a non-volatile MOS transistor of a first conductivity type having a first source/drain connected to a first power supply potential,
a second source/drain connected to an output node, a floating gate, and a control gate, the control gate connected to a non-volatile
control gate node;
a volatile MOS transistor of a second conductivity type having a first source/drain connected to the output node, a second
source/drain connected to a second power supply potential and a control gate connected to a volatile control gate node separate
from the non-volatile control gate node; and
a volatile switch coupled to the output node through a resistor;
wherein an RC time constant of the memory cell is greater than a recovery time of the memory cell.
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