| US 7,589,995 B2 | ||
| One-transistor memory cell with bias gate | ||
| Sanh D. Tang, Boise, Id. (US); Gordon Haller, Boise, Id. (US); and Daniel H. Doyle, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Sep. 07, 2006, as Appl. No. 11/516,814. | ||
| Prior Publication US 2008/0061346 A1, Mar. 13, 2008 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—174 [365/149; 257/E27.091] | 32 Claims |
| 1. A semiconductor device, comprising:
a substrate comprising base single crystalline semiconductor material; and
MOS transistors formed on the base semiconductor material, individual of the MOS transistors including:
a conductive inner bias gate layer within the base single crystalline semiconductor material;
a floating body region over the inner bias gate layer, the floating body region comprising the base single crystalline semiconductor
material;
a drain region coupled to the floating body region, the drain region comprising the base single crystalline semiconductor
material;
a source region coupled to the floating body region, the source region comprising the base single crystalline semiconductor
material; and
a conductive outer gate coupled to the floating body region, the outer gate being recessed from an outer surface of and into
the base single crystalline semiconductor material, the outer gate being received between the drain region and the source
region within the base single crystalline semiconductor material.
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