| US 7,589,992 B2 | ||
| Semiconductor device having three dimensional structure | ||
| Gong-Heum Han, Gyeonggi-do (Korea, Republic of); Hyou-Youn Nam, Gyeonggi-do (Korea, Republic of); Bo-Tak Lim, Gyeonggi-do (Korea, Republic of); Han-Byung Park, Gyeonggi-do (Korea, Republic of); Soon-Moon Jung, Gyeonggi-do (Korea, Republic of); and Hoon Lim, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Dec. 10, 2007, as Appl. No. 11/953,289. | ||
| Application 11/953289 is a continuation of application No. 11/191496, filed on Jul. 28, 2005, granted, now 7,315,466. | ||
| Claims priority of application No. 2004-61527 (KR), filed on Aug. 04, 2004; and application No. 2005-38621 (KR), filed on May 09, 2005. | ||
| Prior Publication US 2008/0089163 A1, Apr. 17, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/189.11; 365/230.06; 365/177] | 43 Claims |
| 1. A semiconductor device, comprising:
a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and
outputting an input signal, respectively;
a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating
an output signal having a high level if at least one of at least two input signals has a low level, respectively; and
a plurality of NOR gates including at least two third pull-up transistor and third pull-down transistor and generating an
output signal having a high level if all of at least two input signals have a low level, respectively
wherein the at least one first pull-up transistor and first pull-down transistor, the at least two second pull-up transistor
and second pull-down transistor, and the at least two third pull-up transistor and third pull-down transistor are stacked
and arranged on at least two layers.
|