| US 7,589,566 B2 | ||
| Semiconductor device provided with antenna ratio countermeasure circuit | ||
| Shigeki Ohbayashi, Tokyo (Japan); Hiroaki Suzuki, Tokyo (Japan); Koichiro Ishibashi, Tokyo (Japan); and Hiroshi Makino, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Dec. 01, 2005, as Appl. No. 11/290,805. | ||
| Claims priority of application No. 2004-351560 (JP), filed on Dec. 03, 2004; and application No. 2005-303160 (JP), filed on Oct. 18, 2005. | ||
| Prior Publication US 2006/0119395 A1, Jun. 08, 2006 | ||
| Int. Cl. H03K 19/00 (2006.01); H01L 25/00 (2006.01); H01L 23/62 (2006.01) | ||
| U.S. Cl. 326—101 [326/121; 257/356; 257/357] | 29 Claims |
| 1. A semiconductor device comprising:
a first well of a first conductivity type formed on a surface of a semiconductor substrate and receiving a first voltage;
a second well of a second conductivity type formed on the surface of said semiconductor substrate and receiving a second voltage;
a logic circuit including a first transistor of the second conductivity type formed on a surface of said first well and receiving
an input signal at its gate and a second transistor of the first conductivity type formed on a surface of said second well
and having its gate connected to the gate of said first transistor;
a first diode formed on the surface of said first well and connected between the gates of said first and second transistors
and said first well;
a second diode formed on the surface of said second well and connected between said second well and the gates of said first
and second transistors; and
a switching element connected between said first and second wells and rendered conductive in response to a voltage between
said first and second wells exceeding a predetermined voltage,
wherein said switching element includes:
a third transistor of the second conductivity type formed on the surface of said first well, having its gate and first electrode
connected to said first well, and having its second electrode connected to said second well, and
a third diode formed on the surface of said first well and interposed between said first well and the first electrode of said
third transistor.
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