| US 7,589,554 B2 | ||
| I/O interface circuit of intergrated circuit | ||
| Shinsuke Hamanaka, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kawasaki, Kanagawa (Japan) | ||
| Filed on Mar. 06, 2008, as Appl. No. 12/73,513. | ||
| Application 12/073513 is a continuation of application No. 10/968114, filed on Oct. 20, 2004, granted, now 7,382,152. | ||
| Claims priority of application No. 2003-363822 (JP), filed on Oct. 23, 2003. | ||
| Prior Publication US 2008/0164905 A1, Jul. 10, 2008 | ||
| Int. Cl. H03K 17/16 (2006.01); H03K 19/003 (2006.01); H03K 5/12 (2006.01) | ||
| U.S. Cl. 326—30 [327/108; 327/170] | 18 Claims |
| 15. A controller for an input/output interface circuit of an integrated circuit having a plurality of transistor pairs which
constitute a primary driver and a secondary driver, and an input/output terminal which is connected to a connection point
of each transistor pair of the plurality of transistor pairs, said controller comprising:
a drive controller controlling switching of each transistor in said plurality of transistor pairs; and
an impedance controller outputting an impedance control signal to the drive controller which generates a control signal for
controlling said secondary driver and for controlling impedance of the secondary driver based on a reference resistance, said
primary driver being controlled other than by said impedance controller,
wherein said drive controller comprises a first NAND gate having as an input an inverted output signal from said integrated
circuit and an output enable signal, and a second NAND gate having as an input said output signal from said integrated circuit
and said output enable signal, said primary driver comprising a transistor pair including a first transistor which is controlled
by an inverted output of said first NAND gate, and a second transistor which is controlled by an output of said second NAND
gate.
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