| US 7,589,552 B1 | ||
| Integrated circuit with redundancy | ||
| Mario E. Guzman, Mountain View, Calif. (US); and Christopher F. Lane, San Jose, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Oct. 23, 2007, as Appl. No. 11/977,293. | ||
| Int. Cl. H03K 19/003 (2006.01) | ||
| U.S. Cl. 326—10 [326/38] | 21 Claims |
| 1. An integrated circuit, comprising:
a plurality of circuit blocks each having spare circuitry and switching circuitry for switching the spare circuitry into use
to repair defects;
a plurality of control circuits that control the switching circuitry based on repair data, wherein each control circuit is
associated with a respective one of the plurality of circuit blocks and has a unique address;
a bus that is connected to each of the plurality of control circuits;
memory that stores the repair data for the circuit blocks; and
a master block repair controller that distributes the repair data from the memory to the plurality of control circuits over
the bus using the unique addresses.
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