| US 7,589,396 B2 | ||
| Chip scale surface mount package for semiconductor device and process of fabricating the same | ||
| Felix Zandman, Bala Cynwyd, Pa. (US); Y. Mohammed Kasem, Santa Clara, Calif. (US); and Yueh-Se Ho, Sunnyvale, Calif. (US) | ||
| Assigned to Vishay-Siliconix, Santa Clara, Calif. (US) | ||
| Filed on Apr. 10, 2007, as Appl. No. 11/786,328. | ||
| Application 11/786328 is a continuation of application No. 11/082080, filed on Mar. 15, 2005, granted, now 7,211,877. | ||
| Application 11/082080 is a continuation of application No. 10/157584, filed on May 28, 2002, granted, now 6,876,061. | ||
| Application 10/157584 is a continuation of application No. 09/395097, filed on Sep. 13, 1999, abandoned. | ||
| Prior Publication US 2007/0235774 A1, Oct. 11, 2007 | ||
| Int. Cl. H01L 29/06 (2006.01); H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—620 | 14 Claims |
| 1. A semiconductor structure comprising:
a conductive substrate;
a first semiconductor die and a second semiconductor die, wherein said first semiconductor die and said second semiconductor
die are coupled to said conductive substrate, and wherein said first semiconductor die and said semiconductor die are separated
by a trench;
a passivation layer on a front side of said first and said second semiconductor die, wherein said passivation layer covers
a portion of said first semiconductor die and a portion of said second semiconductor die; and
a metal layer lining the bottom and walls of said trench and extending onto said passivation layer, wherein said metal layer
lining leaves at least a portion of said passivation layer on said front side of said first and said second semiconductor
die exposed.
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