US 7,589,378 B2
Power LDMOS transistor
Christopher Boguslaw Kocon, Mountain Top, Pa. (US); Shuming Xu, Schnecksville, Pa. (US); and Jacek Korec, Sunrise, Fla. (US)
Assigned to Texas Instruments Lehigh Valley Incorporated, Dallas, Tex. (US)
Filed on Feb. 20, 2007, as Appl. No. 11/676,613.
Application 11/676613 is a continuation in part of application No. 11/180155, filed on Jul. 13, 2005, granted, now 7,282,765.
Prior Publication US 2007/0138548 A1, Jun. 21, 2007
Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/00 (2006.01)
U.S. Cl. 257—343  [257/409] 28 Claims
OG exemplary drawing
 
1. A laterally diffused metal-oxide-semiconductor transistor device comprising:
a substrate having a first conductivity type;
a semiconductor layer formed over said substrate and having lower and upper surfaces;
a source region of the first conductivity type and a lightly-doped drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of said semiconductor layer, said source and lightly-doped drain extension regions being spaced from one another;
a body region of a second conductivity type formed in said semiconductor layer, said body region forming a channel region between said source and lightly-doped drain extension regions and extending under said source region;
a conductive gate formed over a gate dielectric layer formed over said channel region;
a drain contact electrically connecting said lightly-doped drain extension region to said substrate and laterally spaced from said channel region, said drain contact comprising a highly-doped drain contact region formed between said substrate and said lightly-doped drain extension region in said semiconductor layer, wherein a topmost portion of said highly-doped drain contact region is spaced from said upper surface of said semiconductor layer by at least a part of said lightly-doped drain extension region; and
a source contact electrically connecting said source region to said body region.