| US 7,589,377 B2 | ||
| Gate structure with low resistance for high power semiconductor devices | ||
| Mercedes P. Gomez, Temecula, Calif. (US); Emil M. Hanna, Granada Hills, Calif. (US); Wen-Ben Luo, Torrance, Calif. (US); and Qingchun Zhang, Cary, N.C. (US) | ||
| Assigned to The Boeing Company, Chicago, Ill. (US) | ||
| Filed on Oct. 06, 2006, as Appl. No. 11/539,482. | ||
| Prior Publication US 2008/0085591 A1, Apr. 10, 2008 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 257—330 [257/331; 257/333; 257/355; 257/495; 257/497; 257/E21.158; 257/E21.223; 257/E21.429; 257/E21.544; 257/E29.021; 257/E29.118; 257/E29.201; 257/E29.258; 257/E29.264] | 18 Claims |
| 1. A gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising:
a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior
region;
a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region, the doped
poly-silicon layer having side walls and a floor surrounding a doped poly-silicon layer interior region;
a first metal layer deposited adjacent to the doped poly-silicon layer and in the doped poly-silicon layer interior region
on a side opposite from the dielectric layer, the first metal layer having side walls and a floor surrounding a first metal
layer interior region; and
an undoped poly-silicon layer deposited to fill the first metal layer interior region, wherein:
the first metal layer is between the undoped poly-silicon layer and the doped poly-silicon layer; and
the undoped poly-silicon layer is interior to the doped poly-silicon layer.
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