| US 7,589,369 B2 | ||
| Semiconductor constructions | ||
| Gordon A. Haller, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Jul. 30, 2008, as Appl. No. 12/221,178. | ||
| Application 12/221178 is a division of application No. 11/411490, filed on Apr. 25, 2006, granted, now 7,419,871. | ||
| Prior Publication US 2008/0290388 A1, Nov. 27, 2008 | ||
| Int. Cl. H01L 27/108 (2006.01) | ||
| U.S. Cl. 257—296 [257/300; 257/330; 257/401; 257/E21.655; 257/E21.658; 438/242; 438/270; 438/589] | 5 Claims |
| 1. A semiconductor construction, comprising:
a semiconductor substrate having a substantially planar semiconductor surface;
paired transistors having gates recessed into the substantially planar surface, sharing a source/drain region, and having
other source/drain regions besides the shared source/drain region;
a silicon nitride-containing layer over at least a portion of each of the paired transistors, and over part of the shared
source/drain region;
a bitline contact extending through the silicon nitride-containing layer to electrically couple with the shared source/drain
region;
a bitline over the silicon nitride-containing layer and electrically coupled with the bitline contact; and
a pair of capacitors over and in electrical connection with said other source/drain regions; at least one of the capacitors
having an electrically conductive storage node material that directly contacts the silicon nitride-containing layer.
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