US 7,588,968 B1
Linked chip attach and underfill
Edward A Zarbock, Gilbert, Ariz. (US); Ming Lei, Chandler, Ariz. (US); and Sabina Houle, Phoenix, Ariz. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Mar. 31, 2008, as Appl. No. 12/59,047.
Int. Cl. H01L 21/48 (2006.01)
U.S. Cl. 438—127  [438/108; 257/E21.503] 9 Claims
OG exemplary drawing
 
1. A method comprising:
placing an integrated circuit onto a package substrate;
performing reflow to attach the integrated circuit to the package substrate;
maintaining the temperature of the integrated circuit and package assembly at or above a predetermined temperature prior to dispensing an underfill between the package substrate and the integrated circuit;
dispensing an underfill material between the package substrate and the integrated circuit;
curing the underfill material to a first level of curing in the integrated circuit and package assembly;
cooling the underfill material in the integrated circuit and package assembly; and
curing the underfill material to a second level of curing wherein the second level of curing is greater than the first level of curing.