| US 7,588,948 B2 | ||
| Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods | ||
| Ralf Lerner, Erfurt (Germany) | ||
| Assigned to X-FAB Semiconductor Foundries AG, Efert (Germany) | ||
| Appl. No. 10/552,984 PCT Filed Apr. 19, 2004, PCT No. PCT/DE2004/000815 § 371(c)(1), (2), (4) Date Sep. 25, 2006, PCT Pub. No. WO2004/095570, PCT Pub. Date Nov. 04, 2004. |
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| Claims priority of application No. 103 17 748 (DE), filed on Apr. 17, 2003. | ||
| Prior Publication US 2007/0054422 A1, Mar. 08, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—16 [257/E21.522] | 27 Claims |
| 1. A test structure for verifying an isolation trench etching in an SOI wafer, wherein the test structure in the SOI device
comprises, after etching of isolation trenches, a row of islands, each of which is surrounded by a trench, said trenches having
increasing trench width from one island to a next island and including a certain trench width of another isolation trench
of an active circuit away from the test structure;
wherein a portion of the surrounding trench (a,b) of each island shares a common portion with the surrounding trench of the
adjacent island;
wherein the respective common portion—except for an island having a broadest (e) or a narrowest (a) isolation trench—has the
width of the adjacent surrounding trench having a next larger or a next smaller measure of width in the row.
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