| US 7,588,946 B2 | ||
| Controlling system for gate formation of semiconductor devices | ||
| Chia-Tsung Tso, Hsin-Chu (Taiwan); Jiun-Hong Lai, Hsin-Chu (Taiwan); Mei-Jen Wu, Hsin-Chu (Taiwan); Li Te Hsu, Shanhua Township, Tainan County (Taiwan); Pin Chia Su, Tainan (Taiwan); and Po-Zen Chen, Kaohsiung (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Jul. 25, 2005, as Appl. No. 11/188,324. | ||
| Prior Publication US 2007/0020777 A1, Jan. 25, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—9 [438/16; 257/E21.528] | 20 Claims |
| 6. A method of controlling gate formation of a semiconductor device, the method comprising:
measuring a step height of a target wafer; and
determining a trimming time of a mask layer using the step height, wherein the mask layer is trimmed from a top and sides
and wherein the mask layer is used for an over-etching a target gate of the semiconductor device of the target wafer.
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