| US 7,587,698 B1 | ||
| Operational time extension | ||
| Andre Rohe, Palo Alto, Calif. (US); Steven Teig, Menlo Park, Calif. (US); Herman Schmit, Palo Alto, Calif. (US); Jason Redgrave, Mountain View, Calif. (US); and Andrew Caldwell, Santa Clara, Calif. (US) | ||
| Assigned to Tabula Inc., Santa Clara, Calif. (US) | ||
| Filed on May 21, 2007, as Appl. No. 11/751,629. | ||
| Application 11/751629 is a continuation of application No. 11/082200, filed on Mar. 15, 2005, granted, now 7,236,009. | ||
| Claims priority of provisional application 60/632277, filed on Dec. 01, 2004. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 17/50 (2006.01); H03K 19/00 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 716—16 [326/41; 716/18] | 8 Claims |
| 1. A method of designing an integrated circuit (“IC”) with a plurality of configurable circuits that operate in a plurality
of operational cycles, the method comprising:
a) assigning an operation on a signal path to a first operational cycle;
b) identifying that the assignment results in a violation of a timing constraint for the signal path; and
c) rectifying the violation by assigning the operation to both the first operational cycle and a second operational cycle
subsequent to the first.
|