	US 7,587,690 B1
	Method and system for global coverage analysis
Bret Siarkowski, Marlborough, Mass. (US); and Manish Pandey, San Jose, Calif. (US)
Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US)
Filed on Jun. 14, 2006, as Appl. No. 11/454,075.
Application 11/454075 is a continuation in part of application No. 10/836700, filed on Apr. 29, 2004, granted, now 7,216,318.
Claims priority of provisional application 60/466698, filed on Apr. 29, 2003.
Int. Cl. G06F 17/50 (2006.01)

U.S. Cl. 716—4 [716/5; 716/6]

38 Claims

1. A method for performing coverage analysis of a design, comprising:

receiving a list of critical paths and one or more constraint information;

identifying gate-level critical path coverage based at least in part upon gate-level information and the one or more constraint information;

pruning the identified gate-level critical path coverage from the list of critical paths based at least in part upon identified coverage for the gate-level information;

identifying RTL-level critical path coverage based at least in part upon RTL-level information;

pruning the identified RTL-level critical path coverage from the list of critical paths based at least in part upon identified coverage for the RTL-level information;

determining, by using a processor, a global coverage for the design based at least in part upon the pruned list of critical paths; and

storing the global coverage for the design in a volatile or non-volatile computer readable medium or displaying the global coverage for the design on a display device.