| US 7,587,687 B2 | ||
| System and method for incremental synthesis | ||
| Yosinori Watanabe, El Cerrito, Calif. (US); Michael Meyer, Palo Alto, Calif. (US); Luciano Lavagno, Berkeley, Calif. (US); and Alex Kondratyev, Campbell, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Dec. 30, 2005, as Appl. No. 11/324,032. | ||
| Prior Publication US 2007/0157131 A1, Jul. 05, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—3 [716/2] | 10 Claims |
| 1. A method of synthesis of a model representing a design of an integrated circuit, the method comprising:
inputting to a synthesis tool information representing a modified input model of the design at a particular level of abstraction;
inputting user constraints;
inputting to the synthesis tool a state file that includes a record of at least one prior soft constraint choice made by the
tool, in a prior translation of a prior input model of the design to a prior output model representing the design at a lower
level of abstraction, in the absence of a user implementation choice;
using the synthesis tool to translate the information to an output model compliant with the inputted user constraints, representing
the design at a lower level of abstraction, wherein translating the modified input model includes applying in the same manner
the at least one prior soft constraint choice included in the inputted state file if the user constraints do not include a
constraint choice selected by the user that conflicts with the at least one prior soft constraint; and
producing a record of the information input to the synthesis tool that guided the translation of the modified model, the information
including at least one soft constraint choice made by the tool in the course of translating the modified model in the absence
of user implementation choice, into an output state file.
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