| US 7,587,646 B1 | ||
| Test pattern generation in residue networks | ||
| Thomas James Snethen, Endwell, N.Y. (US); and Carolyn Asher, Endicott, N.Y. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Jun. 20, 2008, as Appl. No. 12/143,043. | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—738 [714/727] | 28 Claims |
| 1. A method of generating test pattern sets to test a network of residue circuits, the method comprising:
determining sets of bit vectors that resolve a residue function of respective residue circuits in a logic cone of a processor-readable
representation of the network, the bit vectors containing bit patterns that combine to apply all input patterns to the respective
residue circuits;
assigning at least one vector of the resolved residue functions to one of the residue circuits in an overlapping logic cone
of the network;
propagating the bit vectors through the logic cone and the overlapping logic cone to the inputs of the network by resolving
the residue function of intervening residue circuits with the vectors propagated thereto; and
storing the bit vectors propagated to the inputs of the network as the test pattern sets.
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