| US 7,587,555 B2 | ||
| Program thread synchronization | ||
| Jeań-Francois C. P. Collard, Sunnyvale, Calif. (US); Norman Paul Jouppi, Palo Alto, Calif. (US); and John Morgan Sampson, San Diego, Calif. (US) | ||
| Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US) | ||
| Filed on Nov. 10, 2005, as Appl. No. 11/272,197. | ||
| Prior Publication US 2007/0113233 A1, May 17, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—138 [711/125; 711/126; 711/151; 711/154; 718/101; 718/102; 718/103] | 31 Claims |
| 1. A method comprising:
determining an address in a first memory for data for each thread of a plurality of program threads to be synchronized;
for each thread of the plurality of program threads, halting execution of the thread at a barrier for a determined address
of the first memory, the halting including invalidating a data cache line associated with the determined address, the data
cache line being located in a cache memory other than the first memory; and
resuming execution of the threads.
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