US 7,586,786 B2
Nonvolatile semiconductor memory
Yasuhiko Matsunaga, Yokohama (Japan); Fumitaka Arai, Yokohama (Japan); Makoto Sakuma, Yokohama (Japan); Tadashi Iguchi, Yokohama (Japan); Hisashi Watanobe, Yokkaichi (Japan); and Hiroaki Tsunoda, Yokkaichi (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Apr. 21, 2008, as Appl. No. 12/106,953.
Application 12/106953 is a division of application No. 11/148336, filed on Jun. 09, 2005, granted, now 7,382,649.
Claims priority of application No. 2004-175876 (JP), filed on Jun. 14, 2004.
Prior Publication US 2009/0016108 A1, Jan. 15, 2009
Int. Cl. G11C 11/34 (2006.01)
U.S. Cl. 365—185.17  [365/63; 365/185.05; 365/185.18] 7 Claims
OG exemplary drawing
 
1. A method of reading out data from a nonvolatile semiconductor memory, the memory including
a bit line, a source line being perpendicular to the bit line, a memory cell unit array including a first memory cell unit and a second memory cell unit connected to the first memory cell unit in series along to the bit line, the first memory cell unit including first and second select gate transistors and a plurality of memory cell transistors arranged between the first and the second select gate transistors in series, the second memory cell unit including third and fourth select gate transistors and a plurality of memory cell transistors arranged between the third and the fourth select gate transistors in series, the second select gate transistor of the first memory cell unit connected to the third select gate transistor of the second memory cell unit via an inter-unit diffusion layer, a length of the first memory cell unit being equal to a length of the second memory cell unit, a bit line contact connecting the first select gate transistor of the first memory cell unit and the bit line, and a source line contact connecting the fourth select gate transistor of the second memory cell unit and the source line, wherein, the memory cell unit array is located having a shift length equal to the integral multiple length of the memory cell units aligned in a bit line direction so as to be staggered from each other as compared with adjacent memory cell unit arrays aligned in a source line direction, the method comprising:
applying a first voltage to the bit line contact;
applying a second voltage to the source line contact, wherein the second voltage is substantially smaller than the first voltage;
applying a third voltage to gates of the third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction;
applying a fourth voltage to gates of the plurality of memory cell transistors of the second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and
applying a fifth voltage to gates of the plurality of memory cell transistors of the first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.