| US 7,586,785 B2 | ||
| Non-volatile semiconductor memory device | ||
| Koji Hosono, Yokohama (Japan); Kenichi Imamiya, Tokyo (Japan); and Hiroshi Nakamura, Fujisawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jan. 28, 2008, as Appl. No. 12/20,981. | ||
| Application 12/020981 is a continuation of application No. 11/366110, filed on Mar. 01, 2006, granted, now 7,330,372. | ||
| Application 11/366110 is a continuation of application No. 11/077046, filed on Mar. 09, 2005, granted, now 7,038,946. | ||
| Application 11/077046 is a continuation of application No. 10/918686, filed on Aug. 13, 2004, granted, now 6,882,569. | ||
| Application 10/918686 is a continuation of application No. 10/360586, filed on Feb. 06, 2003, granted, now 6,798,697. | ||
| Claims priority of application No. 2002-029972 (JP), filed on Feb. 06, 2002. | ||
| Prior Publication US 2008/0175052 A1, Jul. 24, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.12 [365/185.18; 365/185.17] | 11 Claims |
| 1. A non-volatile semiconductor memory device comprising:
a memory cell array with electrically erasable and programmable memory cells arranged therein; and
a read/write circuit configured to hold write data, which is to be written into the memory cell array, and read data of the
memory cell array,
wherein said read/write circuit further comprises a plurality of page buffers, each of which including latch circuits in units
of bit lines, said page buffers configured to temporarily hold write/read data,
wherein data read operation for reading out data of the memory cell array to one of the page buffers is so performed as to
interrupt a data write operation for writing data from another one of said page buffers to the memory cell array.
|