| US 7,586,298 B2 | ||
| Chipset for isolated power supply with new programmable synchronization architecture | ||
| Fereydun Tabaian, Newport Coast, Calif. (US); Hamed Sadati, Dubai (United Arab Emirates); and Ali Hejazi, Dubai (United Arab Emirates) | ||
| Assigned to Nupower Semiconductor, Inc., Newport Beach, Calif. (US) | ||
| Filed on Jul. 07, 2008, as Appl. No. 12/168,555. | ||
| Application 12/168555 is a continuation of application No. 11/301187, filed on Dec. 12, 2005, granted, now 7,414,385. | ||
| Claims priority of provisional application 60/634910, filed on Dec. 10, 2004. | ||
| Claims priority of provisional application 60/634858, filed on Dec. 10, 2004. | ||
| Prior Publication US 2008/0266909 A1, Oct. 30, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G05F 1/56 (2006.01) | ||
| U.S. Cl. 323—288 [363/16] | 11 Claims |

| 1. A chipset comprising:
a first primary controller comprising:
control and drive circuitry;
a high speed oscillator having integrated feed forward compensation providing immediate duty cycle adjustment while maintaining
a constant oscillator frequency up to 1 MHz;
a soft start circuit;
a band gap circuit coupled to the soft start circuit to produce an accurate reference;
a pulse width modulation circuit coupled to the soft start circuit;
an output circuit coupled to the pulse width modulation circuit, wherein the output circuit feeds the output of the first
primary controller;
a secondary controller to provide rectification signals coupled to the first primary controller, the secondary controller
comprising:
a band gap circuit for producing an accurate reference coupled to a Schmitt trigger, a comparator, a bias net circuit and
an over-voltage lockout circuit; and
at least two latches coupled to at least two detectors, wherein the latches are coupled to the Schmitt trigger;
a first gate driver connected to the first primary controller; and
a second gate driver connected to the secondary controller;
the first gate driver driving at least two MOSFETs, and
the first primary controller in communication with the secondary controller.
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