| US 7,586,293 B2 | ||
| Digital modulation circuit | ||
| Man Suk Seo, Gyunggi-do (Korea, Republic of); Hyung Cheol Park, Daejeon (Korea, Republic of); Seong Soo Lee, Gyunggi-do (Korea, Republic of); Sang Yub Lee, Gyunggi-do (Korea, Republic of); Chang Soo Yang, Gyunggi-do (Korea, Republic of); and Wan Cheol Yang, Gyunggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electro-Mechanics Co., Ltd., Suwon, Gyunggi-Do (Korea, Republic of) | ||
| Filed on Aug. 30, 2007, as Appl. No. 11/847,761. | ||
| Claims priority of application No. 10-2006-0083566 (KR), filed on Aug. 31, 2006. | ||
| Prior Publication US 2008/0055139 A1, Mar. 06, 2008 | ||
| Int. Cl. H04L 27/20 (2006.01) | ||
| U.S. Cl. 322—105 [322/103; 322/112; 322/113; 375/146; 375/239; 375/308] | 8 Claims |
| 1. A digital modulation circuit, comprising:
a clock generator which generates a reference clock pulse having a predetermined period;
an up/down counter which generates a count value having predetermined bits by up-counting or down-counting the reference clock
pulse and outputs a bit in the count value as a transmission signal;
a controller which determines a counting start/end time point of the up/down counter and determines which one of the up-counting
operation and the down-counting operation of the up/down counter is to be performed, according to a value of digital transmission
data that is to be transmitted; and
a band-pass filter which converts a waveform of the transmission signal output from the up/down counter into a sine waveform.
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