| US 7,586,130 B2 | ||
| Vertical field effect transistor using linear structure as a channel region and method for fabricating the same | ||
| Takahiro Kawashima, Osaka (Japan); Tohru Saitoh, Ibaraki (Japan); and Takeshi Takagi, Kyoto (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Feb. 01, 2006, as Appl. No. 11/344,574. | ||
| Application 11/344574 is a continuation of application No. PCT/JP2005/017830, filed on Sep. 28, 2005. | ||
| Claims priority of application No. 2004-291170 (JP), filed on Oct. 04, 2004. | ||
| Prior Publication US 2006/0125025 A1, Jun. 15, 2006 | ||
| Int. Cl. H01L 29/732 (2006.01) | ||
| U.S. Cl. 257—135 [977/938; 257/401; 257/288; 257/368; 257/242; 257/263; 257/302; 257/328; 257/329; 257/E27.02; 257/E27.022; 257/E27.031; 257/E27.038; 257/E27.039; 257/E27.041; 257/E27.042; 257/E27.054; 257/E27.055; 257/E27.056; 257/E27.057; 257/E27.058; 257/E27.096; 257/E29.118; 257/E29.131; 257/E29.183; 257/E29.186; 257/E29.189; 257/E29.198; 257/E29.257; 257/E29.262; 257/E29.274; 257/E29.313; 257/E29.318; 257/E21.375; 257/E21.41; 257/E21.447; 257/E21.612; 257/E21.676] | 27 Claims |
| 1. A vertical field effect transistor comprising:
a bundle of multiple linear structures, which functions as a channel region where electric carriers are transported;
a lower electrode, which is connected to the bottom of the bundle of multiple linear structures and which functions as one
of source and drain regions;
an upper electrode, which is connected to the top of the bundle of multiple linear structures and which functions as the other
of the source and drain regions;
a gate electrode for controlling the electric conductivity of at least a portion of the bundle of multiple linear structures;
and
a gate insulating film, which is arranged between the bundle of multiple linear structures and the gate electrode in order
to electrically isolate the gate electrode from the bundle of multiple linear structures,
wherein the transistor further includes a dielectric layer which supports the upper electrode, the dielectric layer having
an outer peripheral side surface,
wherein the upper electrode is located over the lower electrode with the dielectric layer interposed between the upper and
lower electrodes, and includes an overhanging end portion that sticks out laterally from over the dielectric layer,
wherein the bundle of multiple linear structures is located right under the overhanging end portion of the upper electrode
and outside of the outer peripheral side surface of the dielectric layer, and
wherein the bundle of multiple linear structures is in contact with the overhanging end portion of the upper electrode, and
the dielectric layer is not in contact with the overhanging end portion of the upper electrode.
|