| US 7,585,793 B2 | ||
| Method for applying a high temperature heat treatment to a semiconductor wafer | ||
| Christophe Maleville, La Terrasse (France); Walter Schwarzenbach, Saint Nazaire Les Eymes (France); and Vivien Renauld, Pontcharra (France) | ||
| Assigned to S.O.I.Tec Silicon on Insulator Technologies, Bernin (France) | ||
| Filed on Sep. 29, 2006, as Appl. No. 11/529,959. | ||
| Application 11/529959 is a continuation of application No. PCT/IB2005/000492, filed on Feb. 03, 2005. | ||
| Prior Publication US 2007/0026692 A1, Feb. 01, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—799 [438/406; 257/506; 257/E21.561; 257/E27.112] | 15 Claims |
| 1. A method for reducing tearing-off defects when applying a high temperature (HT) heat treatment to a semiconductor wafer
that comprises a silicon-on-insulator (SOI) structure, which method comprises:
providing a heating chamber for conducting a HT heat treatment of the SOI semiconductor wafer, wherein the heating chamber
is initially provided at an initial heating temperature;
providing the SOI semiconductor wafer at a first temperature for introduction into the heating chamber; and
ramping-up the initial temperature of the heating chamber to conduct the HT heat treatment;
wherein during the HT heat treatment, either the first temperature of the SOI semiconductor wafer is provided at a lower temperature
below 600° C., or the ramping-up temperature of the heating chamber is provided at a rate slower than 10° C./min, or both
are provided, so that the resulting heat treated wafer exhibits reduced tearing-off defects compared to silicon-on-insulator
wafers treated by a conventional HT heat treatment.
|