US 7,585,748 B2
	Process for manufacturing a multilayer structure made from semiconducting materials
Jean-Pierre Raskin, Saint Germain (Belgium); Dimitri Lederer, Ernage (Belgium); and François Brunier, Grenoble (France)
Assigned to S.O.I.Tec Silicon on Insulator Technologies, Bernin (France); and Université Catholique de Louvain, Louvain-la-Neuve (Belgium)
Filed on Mar. 24, 2006, as Appl. No. 11/389,469.
Application 11/389469 is a continuation of application No. PCT/IB2004/003340, filed on Sep. 27, 2004.
Claims priority of application No. 03 11347 (FR), filed on Sep. 26, 2003.
Prior Publication US 2006/0166451 A1, Jul. 27, 2006
Int. Cl. H01L 21/30 (2006.01); H01L 21/46 (2006.01)

U.S. Cl. 438—455  [257/E21.567]

20 Claims

1. A process for manufacturing a multilayer structure made of semiconducting materials and comprising an active layer, a support layer and an electrically insulating layer between the active layer and the support layer, which comprises modifying properties of the electrically insulating layer in order to minimize electrical losses in the support layer and enhance signal quality in the active layer.