| US 7,585,739 B2 | ||
| Semiconductor device and method of fabricating the same | ||
| Takashi Saiki, Kawasaki (Japan); Hiroyuki Ohta, Kawasaki (Japan); and Hiroyuki Kanata, Kawasaki (Japan) | ||
| Assigned to Fujitsu Microelectronics Limited, Tokyo (Japan) | ||
| Filed on Nov. 21, 2007, as Appl. No. 11/984,737. | ||
| Application 11/984737 is a division of application No. 10/800749, filed on Mar. 16, 2004, granted, now 7,321,151. | ||
| Claims priority of application No. 2003-373499 (JP), filed on Oct. 31, 2003. | ||
| Prior Publication US 2008/0206948 A1, Aug. 28, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—306 [438/519; 257/E21.618; 257/E21.619; 257/E21.634] | 8 Claims |
| 1. A method of fabricating a semiconductor device comprising the stops of:
forming a gate over a semiconductor region through an insulating film:
forming a first impurity-diffused region by introducing an impurity into a surficial layer of said semiconductor region under
masking by said gate;
forming a first sidewall spacer over both lateral faces of said gate;
forming a third impurity-diffused region by introducing a diffusion suppressive element into the surficial layer of said semiconductor
region under masking by said gate and said first sidewall spacer;
forming a second sidewall spacer to cover said first sidewall spacer over both lateral sides of said gate; and
forming a second impurity-diffused region by introducing an impurity into the surficial layer of said semiconductor region
to a depth larger than that of said first impurity-diffused region under masking by said gate, said first sidewall spacer
and said second sidewall spacer,
wherein said diffusion suppressive element is any one element selected from nitrogen, fluorine and carbon, and wherein the
third impurity-diffused region is amorphous.
|