| US 7,585,710 B2 | ||
| Methods of forming electronic devices having partially elevated source/drain structures | ||
| Min-Cheol Park, Seoul (Korea, Republic of); and Sung-Hoi Hur, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co, Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Dec. 14, 2006, as Appl. No. 11/638,775. | ||
| Application 11/638775 is a division of application No. 11/020311, filed on Dec. 22, 2004. | ||
| Prior Publication US 2007/0090466 A1, Apr. 26, 2007 | ||
| Int. Cl. H01L 29/72 (2006.01) | ||
| U.S. Cl. 438—151 [438/197; 438/672; 438/675; 257/330] | 5 Claims |

| 1. A method of fabricating a transistor, comprising:
forming a gate layer on a semiconductor substrate;
implanting low-concentrated impurities into the semiconductor substrate around both sides of the gate layer to form a low-concentrated
diffusion region;
forming an inter-level insulation film on an entire surface of the semiconductor substrate on which the low-concentrated diffusion
region is formed;
patterning the inter-level insulation film to form contact holes exposing the semiconductor substrate on which the low-concentrated
diffusion region is formed;
growing an epitaxial layer on the semiconductor substrate exposed by the contact holes; and
forming a contact pattern to fill the contact holes;
wherein during the growth of the epitaxial layer, impurities are implanted while gradually increasing a concentration of the
impurities so that an impurity dopant concentration of the epitaxial layer increases with increasing distance from the semiconductor
substrate.
|