US 11,744,072 B2
Integrated assemblies which include stacked memory decks
John D. Hopkins, Meridian, ID (US); Justin B. Dorhout, Boise, ID (US); Nirup Bandaru, Boise, ID (US); Damir Fazil, Boise, ID (US); Nancy M. Lomeli, Boise, ID (US); Jivaan Kishore Jhothiraman, Meridian, ID (US); and Purnima Narayanan, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 2, 2021, as Appl. No. 17/391,453.
Application 17/391,453 is a division of application No. 16/700,877, filed on Dec. 2, 2019, granted, now 11,107,831.
Prior Publication US 2021/0358951 A1, Nov. 18, 2021
Int. Cl. H10B 41/10 (2023.01); H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 21 Claims
OG exemplary drawing
 
1. An integrated assembly, comprising:
a first deck having first memory cells arranged in first tiers disposed one atop another; the first deck having first inner lateral edges;
a second deck over the first deck; the second deck having second memory cells arranged in second tiers disposed one atop another; the second deck having second inner lateral edges;
an inter-deck structure between the first and second decks and comprising etch-stop material against the first deck; the inter-deck structure having an inter-deck material with third inner lateral edges which are laterally offset relative to the first and second inner lateral edges to leave cavities between the first and second decks; and
a pillar passing through the first and second decks and the inter-deck structure; the pillar comprising channel material, tunneling material, charge-storage material, charge-blocking material and dielectric-barrier material.