CPC H04L 9/3247 (2013.01) [G06F 16/2336 (2019.01); G06F 30/331 (2020.01); H04L 9/321 (2013.01); H04L 9/50 (2022.05); H04L 2209/125 (2013.01)] | 20 Claims |
1. A hardware accelerator, comprising:
circuitry configured to:
receive a block of transactions to be committed to a ledger of a blockchain;
verify a signature of the block using a block verify;
validate each of the transactions in the block using a block validate, wherein the block verify and the block validate are pipelined at a block level such that the block verify is configured to verify a signature of a first block in parallel with the block validate validating each of the transactions in a second block, wherein the first and second blocks are received at the hardware accelerator at different times, wherein the first and second blocks contain different sets of transactions; and
store validation results of the transactions,
wherein one of a processor in a computing system or the hardware accelerator is configured to commit the transactions to the ledger.
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