CPC H03K 19/17784 (2013.01) [H03K 5/135 (2013.01); H03K 19/01742 (2013.01); H04L 25/03878 (2013.01)] | 14 Claims |
1. A method for optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method, comprising:
setting a ratio and sizes of a pull-up NMOS transistor and a pull-down NMOS transistor included in an N-over-N driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and
setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern,
wherein the N-over-N driver includes a plurality of pull-up NMOS transistors and a plurality of pull-down NMOS transistors, each of the pull-up transistors and the pull-down transistors having a binary size, and
wherein the ratio and sizes of the pull-up NMOS transistor and the pull-down NMOS transistor is determined by selecting one or more pull-up transistors or one or more pull-down transistors from among the plurality of pull-up transistors and the plurality of pull-down transistors.
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