US 11,742,859 B2
Method and apparatus for optimizing memory power
Deog Kyoon Jeong, Seoul (KR); Jung Hun Park, Seoul (KR); Kwang Hoon Lee, Seoul (KR); and Yong Jae Lee, Seoul (KR)
Assigned to SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, Seoul (KR)
Filed by SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, Seoul (KR)
Filed on Dec. 21, 2021, as Appl. No. 17/558,036.
Claims priority of application No. 10-2021-0133311 (KR), filed on Oct. 7, 2021.
Prior Publication US 2023/0113660 A1, Apr. 13, 2023
Int. Cl. H04L 25/49 (2006.01); H03K 19/17784 (2020.01); H04L 25/03 (2006.01); H03K 5/135 (2006.01); H03K 19/017 (2006.01)
CPC H03K 19/17784 (2013.01) [H03K 5/135 (2013.01); H03K 19/01742 (2013.01); H04L 25/03878 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method, comprising:
setting a ratio and sizes of a pull-up NMOS transistor and a pull-down NMOS transistor included in an N-over-N driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and
setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern,
wherein the N-over-N driver includes a plurality of pull-up NMOS transistors and a plurality of pull-down NMOS transistors, each of the pull-up transistors and the pull-down transistors having a binary size, and
wherein the ratio and sizes of the pull-up NMOS transistor and the pull-down NMOS transistor is determined by selecting one or more pull-up transistors or one or more pull-down transistors from among the plurality of pull-up transistors and the plurality of pull-down transistors.