	US 11,742,345 B2
	Method of forming an array of multi-stack nanosheet structures having a dam structure isolating multi-stack transistors
Inchan Hwang, Schenectady, NY (US); and Hwichan Jun, Clifton Park, NY (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 15, 2022, as Appl. No. 17/866,066.
Application 17/866,066 is a continuation of application No. 17/147,587, filed on Jan. 13, 2021, granted, now 11,437,369.
Claims priority of provisional application 63/086,766, filed on Oct. 2, 2020.
Prior Publication US 2022/0359500 A1, Nov. 10, 2022
Int. Cl. H01L 21/822 (2006.01); H01L 27/085 (2006.01); H01L 21/8234 (2006.01)

CPC H01L 27/085 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01)]

11 Claims

1. A method of manufacturing an array of multi-stack transistor structures, the method comprising:

providing the multi-stack transistor structures arranged in a plurality of rows and a plurality of columns in the array, each of the multi-stack transistor structures comprising a 1st transistor stack and a 2^ndtransistor stack formed above the 1^sttransistor stack;

performing gate-cut patterning along a plurality of 1^stlines dividing the multi-stack transistor structures by row to form a plurality of 1^sttrenches;

forming a dam structure in the 1^sttrenches to isolate multi-stack transistor structures in one row from multi-stack transistor structures in an adjacent row in the array; and

after the forming the dam structure, forming at least a 1^stsource/drain contact structure landing on a 1^stsource/drain region of the 1^sttransistor stack of each of the multi-stack transistor structures.