US 11,742,280 B2
Integrated circuits with backside power rails
Chih-Chao Chou, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Shi Ning Ju, Hsinchu (TW); Wen-Ting Lan, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 8, 2022, as Appl. No. 17/860,253.
Application 17/093,303 is a division of application No. 16/427,831, filed on May 31, 2019, granted, now 10,833,003, issued on Nov. 10, 2020.
Application 17/860,253 is a continuation of application No. 17/093,303, filed on Nov. 9, 2020, granted, now 11,387,181.
Prior Publication US 2022/0344254 A1, Oct. 27, 2022
Int. Cl. H01L 23/50 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01)
CPC H01L 23/50 (2013.01) [H01L 27/0886 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device structure, comprising:
a first semiconductor layer;
a second semiconductor layer on the first semiconductor layer, the second semiconductor layer being different from the first semiconductor layer in terms of composition;
a first fin and a second fin extending from the second semiconductor layer along a first direction;
a first source/drain feature disposed on the first fin;
a second source/drain feature disposed on the second fin; and
a backside metal layer extending through the first semiconductor layer and the second semiconductor layer,
wherein a portion of the backside metal layer extends above the second semiconductor layer such that the portion is disposed between the first fin and the second fin along a second direction perpendicular to the first direction,
wherein the backside metal layer is spaced apart from the first semiconductor layer, the second semiconductor layer, a sidewall of the first fin, and a sidewall of the second fin by a first dielectric layer.