US 11,742,277 B2
Packaged integrated device having memory buffer integrated circuit asymmetrically positioned on substrate
Shahram Nikoukary, Mountain View, CA (US); Jonghyun Cho, Santa Clara, CA (US); Nitin Juneja, Fremont, CA (US); and Ming Li, Fremont, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Appl. No. 17/264,231
Filed by Rambus Inc., San Jose, CA (US)
PCT Filed Aug. 12, 2019, PCT No. PCT/US2019/046176
§ 371(c)(1), (2) Date Jan. 28, 2021,
PCT Pub. No. WO2020/036878, PCT Pub. Date Feb. 20, 2020.
Claims priority of provisional application 62/795,968, filed on Jan. 23, 2019.
Claims priority of provisional application 62/718,726, filed on Aug. 14, 2018.
Prior Publication US 2021/0305142 A1, Sep. 30, 2021
Int. Cl. H01L 23/498 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 23/49816 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A packaged integrated device, comprising:
a package substrate having a first plurality of connection conductors and a second plurality of connection conductors, the first plurality of connection conductors and the second plurality of connection conductors comprising solder balls;
the package substrate having a surface that is substantially rectangular, the substantially rectangular surface having a first edge and a second edge, the first edge and the second edge defining a package centerline that is substantially parallel to the first edge and the second edge and substantially equidistant between the first edge and the second edge;
a memory buffer integrated circuit die mounted to the surface, the memory buffer integrated circuit die having a first plurality of die connections connected to the first plurality of connection conductors via a first plurality of signal conductors, the memory buffer integrated circuit die having a second plurality of die connections connected to the second plurality of connection conductors via a second plurality of signal conductors, the memory buffer integrated circuit die configured to receive at least a first plurality of command/address signals from a host via the first plurality of die connections, the memory buffer integrated circuit die configured to transmit a second plurality of command/address signals to at least one memory device via the second plurality of die connections;
the first plurality of connection conductors disposed between the package centerline and the first edge, the second plurality of connection conductors disposed between the first plurality of connection conductors and the second edge; and
the memory buffer integrated circuit die disposed such that a first average distance from the memory buffer integrated circuit die to the first plurality of connection conductors is less than a second average distance from the memory buffer integrated circuit die to the second plurality of connection conductors.