US 11,742,271 B2
Semiconductor package
Gyuho Kang, Cheonan-si (KR); Seong-Hoon Bae, Cheonan-si (KR); Jin Ho An, Seoul (KR); Teahwa Jeong, Hwaseong-si (KR); Ju-Il Choi, Seongnam-si (KR); and Atsushi Fujisaki, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 4, 2021, as Appl. No. 17/306,988.
Claims priority of application No. 10-2020-0114829 (KR), filed on Sep. 8, 2020.
Prior Publication US 2022/0077043 A1, Mar. 10, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05015 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/182 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a redistribution substrate including a redistribution pattern;
a semiconductor chip mounted on a top surface of the redistribution substrate; and
a connection terminal between the semiconductor chip and the redistribution substrate,
wherein the redistribution substrate further comprises
a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal,
a shaped insulating pattern disposed on a top surface of the redistribution pattern between the pad via and the redistribution pattern, and
a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.