US 11,742,220 B2
Integrated passive device package and methods of forming same
Feng-Cheng Hsu, New Taipei (TW); Shuo-Mao Chen, New Taipei (TW); Jui-Pin Hung, Hsinchu (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 10, 2022, as Appl. No. 17/669,184.
Application 17/669,184 is a continuation of application No. 16/690,955, filed on Nov. 21, 2019, granted, now 11,251,054.
Application 16/690,955 is a continuation of application No. 15/911,893, filed on Mar. 5, 2018, granted, now 10,504,752, issued on Dec. 10, 2019.
Application 15/911,893 is a continuation of application No. 15/225,083, filed on Aug. 1, 2016, granted, now 9,911,629, issued on Mar. 6, 2018.
Claims priority of provisional application 62/293,724, filed on Feb. 10, 2016.
Prior Publication US 2022/0165587 A1, May 26, 2022
Int. Cl. H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 21/683 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 21/568 (2013.01) [H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/00 (2013.01); H01L 24/02 (2013.01); H01L 24/19 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 25/00 (2013.01); H01L 21/561 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/18 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a die comprising a plurality of contacts extending above a top surface of the die;
a redistribution structure directly connected to the plurality of die contacts, wherein the redistribution structure includes a routing layer width that is wider than the die;
one or more solder bumps connected to the redistribution structure, wherein the redistribution structure is between the die and the one or more solder bumps;
at least one peripheral component located laterally adjacent to the die and attached to the redistribution structure; and
an encapsulant covering the die, covering the at least one peripheral component, and surrounding the plurality of die contacts, the encapsulant extending laterally to the same width as the redistribution structure.