CPC G11C 29/025 (2013.01) [G11C 5/063 (2013.01); G11C 7/1048 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/06 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01)] | 20 Claims |
1. A memory system comprising:
a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip; and a controller configured to control the NVM,
wherein the controller comprises:
a data pin configured to receive read data through a data bus during a read operation;
a data strobe pin configured to receive a data strobe signal through a data strobe signal bus during the read operation;
a read enable pin configured to transmit a read enable signal through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section; and
an on-die termination (ODT) pin configured to transmit an ODT signal during the read operation,
wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, and the read enable signal bus of the NVM, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform the ODT when the read data is read from the second NVM chip.
|