US 11,741,904 B2
High frame rate display
Ting-Kuo Chang, San Jose, CA (US); Abbas Jamshidi Roudbari, Saratoga, CA (US); Tsung-Ting Tsai, San Jose, CA (US); Warren S. Rieutort-Louis, Cupertino, CA (US); Shinya Ono, Santa Clara, CA (US); Shin-Hung Yeh, Taipei (TW); Chien-Ya Lee, Taipei (TW); and Shyuan Yang, Burlingame, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 19, 2021, as Appl. No. 17/206,425.
Application 17/206,425 is a continuation in part of application No. 16/120,076, filed on Aug. 31, 2018, granted, now 10,984,727.
Claims priority of provisional application 62/561,583, filed on Sep. 21, 2017.
Prior Publication US 2021/0210022 A1, Jul. 8, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3275 (2016.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3275 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 2310/021 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display comprising:
an array of pixels;
gate lines configured to supply gate signals to rows of pixels in the array;
data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each having one of the odd data lines and an adjacent one of the even data lines, and wherein each column of pixels in the array includes a respective one of the pairs of data lines;
demultiplexer circuitry coupled to the data lines; and
display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide each column of pixels in the array with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry is configured to operate alternately in:
a first mode in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines while the display driver circuitry asserts a first of the gate lines coupled to a first row of pixels in the array; and
a second mode in which the demultiplexer circuitry provides data from the display driver circuitry to the even data lines while the display driver circuitry asserts a second of the gate lines coupled to a second row of pixels in the array.