US 11,741,284 B2
Systems and methods of automatic generation of integrated circuit IP blocks
Danny Rittman, Oceanside, CA (US); and Mo Jacob, Beverly Hills, CA (US)
Assigned to GBT Technologies, Inc., Santa Monica, CA (US)
Filed by GBT Technologies Inc., Santa Monica, CA (US)
Filed on Sep. 27, 2022, as Appl. No. 17/953,378.
Claims priority of provisional application 63/249,150, filed on Sep. 28, 2021.
Prior Publication US 2023/0097030 A1, Mar. 30, 2023
Int. Cl. G06F 30/39 (2020.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/398 (2020.01); G06F 30/17 (2020.01); G06F 115/08 (2020.01)
CPC G06F 30/39 (2020.01) [G06F 30/17 (2020.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/398 (2020.01); G06F 2115/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method of automatically generating an electronic circuit IP block, comprising:
obtaining manufacturing processes and design rules from an external source;
defining an electronic circuit to be fabricated;
preparing a circuit schematic of the defined electronic circuit, the circuit schematic containing electrical information and constraints corresponding to the defined electronic circuit; and
generating an IP block for the defined electronic circuit based on the circuit schematic, the IP block being compliant with the manufacturing processes, design rules, electrical information, and constraints.