US 11,741,015 B2
Fault buffer for tracking page faults in unified virtual memory system
Jerome F. Duluk, Jr., Palo Alto, CA (US); Cameron Buschardt, Round Rock, TX (US); Sherry Cheung, San Jose, CA (US); James Leroy Deming, Madison, AL (US); Samuel H. Duncan, Arlington, MA (US); Lucien Dunning, Santa Clara, CA (US); Robert George, Austin, TX (US); Arvind Gopalakrishnan, San Jose, CA (US); Mark Hairgrove, San Jose, CA (US); Chenghuan Jia, Fremont, CA (US); and John Mashey, Portola Valley, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Aug. 18, 2022, as Appl. No. 17/820,870.
Application 17/820,870 is a continuation of application No. 14/055,345, filed on Oct. 16, 2013, granted, now 11,487,673.
Claims priority of provisional application 61/782,349, filed on Mar. 14, 2013.
Claims priority of provisional application 61/800,004, filed on Mar. 15, 2013.
Prior Publication US 2022/0405211 A1, Dec. 22, 2022
Int. Cl. G06F 11/07 (2006.01); G06F 12/08 (2016.01); G06F 12/1072 (2016.01); G06F 12/109 (2016.01); G06F 12/12 (2016.01); G06F 12/10 (2016.01); G06F 12/1009 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 11/073 (2013.01); G06F 11/0793 (2013.01); G06F 12/08 (2013.01); G06F 12/109 (2013.01); G06F 12/1072 (2013.01); G06F 12/12 (2013.01); G06F 12/10 (2013.01); G06F 2212/1016 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A computer system, comprising:
a first processor;
a system memory that is coupled to first processor and includes a page state directory;
a second processor; and
a local memory that is coupled to the second processor,
wherein the page state director includes a plurality of virtual address-to-physical address mappings for a plurality of memory pages that are accessible via a virtual memory address space,
wherein the page state directory is coupled to a first page table associated with the first processor, the first page table including one or more virtual-to-physical address mappings for one or more memory pages included in the plurality of memory pages to which the first processor has access,
wherein the page state directory is coupled to a second page table associated with the second processor, the second page table including one or more virtual-to-physical address mappings for one or more memory pages included in the plurality of memory pages to which the second processor has access, and
wherein an application, when executed by the first processor, can access any memory page included in the plurality of memory pages via a pointer that points to different virtual addresses across the virtual memory address space.