US 11,740,968 B2
Error correction hardware with fault detection
Saket Jalan, Karnataka (IN); Indu Prathapan, Karnataka (IN); and Abhishek Ganapati Karkisaval, Karnataka (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 25, 2022, as Appl. No. 17/824,605.
Application 15/844,259 is a division of application No. 15/244,739, filed on Aug. 23, 2016, granted, now 9,904,595, issued on Feb. 27, 2018.
Application 17/824,605 is a continuation of application No. 16/790,444, filed on Feb. 13, 2020, granted, now 11,372,715.
Application 16/790,444 is a continuation of application No. 15/844,259, filed on Dec. 15, 2017, granted, now 10,599,514, issued on Mar. 24, 2020.
Prior Publication US 2022/0283899 A1, Sep. 8, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1012 (2013.01); G06F 11/1048 (2013.01); G11C 29/52 (2013.01)] 34 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a comparison signal from a comparator, where the comparison signal indicates a comparison between an output of a first error correction code (ECC) logic in read path circuitry to an output of a second ECC logic in write path circuitry;
detecting, based on the comparison signal, a fault in the second ECC logic or in the first ECC logic when the output of the second ECC logic does not equal the output of the first ECC logic;
when said fault is a single-bit error, correcting said single-bit error; and
when said fault is a multi-bit error, sending a multi-bit error interrupt signal.