CPC G06F 11/1068 (2013.01) [G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1012 (2013.01); G06F 11/1048 (2013.01); G11C 29/52 (2013.01)] | 34 Claims |
1. A method comprising:
receiving a comparison signal from a comparator, where the comparison signal indicates a comparison between an output of a first error correction code (ECC) logic in read path circuitry to an output of a second ECC logic in write path circuitry;
detecting, based on the comparison signal, a fault in the second ECC logic or in the first ECC logic when the output of the second ECC logic does not equal the output of the first ECC logic;
when said fault is a single-bit error, correcting said single-bit error; and
when said fault is a multi-bit error, sending a multi-bit error interrupt signal.
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