| US 7,584,317 B2 | ||
| Protocol conversion circuit | ||
| Yuki Sakai, Kawasaki (Japan); and Katsuhiro Yoda, Kawasaki (Japan) | ||
| Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
| Filed on Aug. 14, 2007, as Appl. No. 11/889,484. | ||
| Application 11/889484 is a continuation of application No. PCT/JP2005/002283, filed on Feb. 15, 2005. | ||
| Prior Publication US 2008/0040521 A1, Feb. 14, 2008 | ||
| Int. Cl. G06F 13/36 (2006.01); G06F 15/16 (2006.01) | ||
| U.S. Cl. 710—315 [713/400; 713/401; 714/814; 714/815; 709/230; 455/422.1] | 12 Claims |
| 1. A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a reconfigurable circuit
provided in a succeeding stage, comprising:
a data storing unit to store input data from the preceding stage circuit;
an output enable signal generating unit to generate an output enable signal for outputting data stored in the data storing
unit to the reconfigurable circuit on a basis of configuration information of the reconfigurable circuit;
an address specifying unit to specify an address for read of an output data for the data storing unit based on the output
enable signal; and
a start signal generating unit to output a start signal to the output enable signal generating unit at a time point when storing
of an initial input data is started for a time interval externally specified in the data storing unit, wherein
the output enable signal generating unit generates an output enable signal which is delayed, by a number of clocks specified
with a parameter, from an input time point of the start signal.
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