US 7,583,948 B2
Time constant automatic adjusting circuit, filter circuit system, and method of automatically adjusting time constant
Osamu Watanabe, Kanagawa (Japan); Rui Ito, Kanagawa (Japan); Shigehito Saigusa, Kanagawa (Japan); and Tetsuro Itakura, Tokyo (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Apr. 27, 2006, as Appl. No. 11/411,939.
Claims priority of application No. 2005-132411 (JP), filed on Apr. 28, 2005.
Prior Publication US 2006/0245132 A1, Nov. 02, 2006
Int. Cl. H04B 1/00 (2006.01)
U.S. Cl. 455—307  [455/258; 455/255; 331/108 B; 331/34; 331/137] 14 Claims
OG exemplary drawing
 
1. A time constant automatic adjusting circuit for adjusting a time constant of a filter circuit to which clock signal is input and which outputs filtered signal, the time constant is variable, comprising:
a phase comparison circuit configured to generate output voltage according to a result of comparing a phase of a filtered signal with the phase of the clock signal;
a first comparator configured to compare the output voltage with a first predetermined voltage;
a second comparator configured to compare the output voltage with a second predetermined voltage, the second predetermined voltage is bigger than the first predetermined voltage;
a third comparator configured to compare the output voltage with a third predetermined voltage, the third predetermined voltage is bigger than the second predetermined voltage;
an up-down counter configured to generate counted bit signal according to the result of the first comparator, the second comparator, and the third comparator; and
a control circuit configured to adjust the time constant of the filter circuit in accordance with the counted bit signal;
wherein, the up-down counter adds first value to the counted bit signal when the output voltage is bigger than the first predetermined voltage,
the up-down counter adds second value which is smaller than the first value to the counted bit signal when the output voltage is between the first predetermined voltage and the second predetermined voltage, and
the up-down counter subtracts third value from the counted bit signal when the output voltage is smaller than the third predetermined voltage.