wherein each of the plurality of sense amplifier portions comprises:

a bit line potential supply line to which a bit line potential is supplied;

a transistor that is connected to the bit line potential supply line and is turned on when a signal level of a precharge signal is in an active state, thereby to supply the bit line potential to a bit line pair in a corresponding column of a memory cell array; and

a gate electrode for supplying the precharge signal to a gate of the transistor;

wherein the gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array, and

wherein a gate-electrode portion is ring-shaped, said gate electrode portion being a connected portion between the gate electrode in a k-th sense amplifier portion among the plurality of sense amplifier portions and the gate electrode in a (k+1)-th sense amplifier portion, k being an odd number.