| US 7,583,270 B2 | ||
| Image processing apparatus | ||
| Mutsuhiro Ohmori, Kanagawa (Japan); and Toshio Horioka, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, (Japan) | ||
| Filed on Feb. 22, 2001, as Appl. No. 9/789,597. | ||
| Application 09/789597 is a continuation of application No. 09/260031, filed on Mar. 02, 1999, granted, now 6,803,918. | ||
| Prior Publication US 2002/0033829 A1, Mar. 21, 2002 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 345—564 [345/572] | 2 Claims |
| 1. An image processing apparatus comprising:
a memory circuit, a distributor, a plurality of address converters, a plurality of memory controllers and a read controller,
said memory circuit storing a set of pixel data,
said memory circuit having a plurality of modules,
each of said plurality of modules having a plurality of banks, each of said plurality of banks being separately addressable
for storing pixel data therein,
each pixel data of said set of pixel data stored within said plurality of banks being simultaneously accessible,
said distributor providing image data and a write address to said plurality of address converters,
an address converter of said plurality of address converters converting said write address to a module address for a module
of said plurality of modules,
a memory controller of said plurality of memory controllers controlling said memory circuit to provide said image data to
said bank as said pixel data,
a read controller controlling said memory controller to receive said pixel data from said bank.
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