| US 7,582,955 B2 | ||
| Semiconductor device manufacturing method and manufacturing apparatus | ||
| Munehide Saimen, Sakata (Japan) | ||
| Assigned to Seiko Epson Corporation, (Japan) | ||
| Filed on Nov. 29, 2007, as Appl. No. 11/998,357. | ||
| Application 11/998357 is a division of application No. 10/985667, filed on Nov. 11, 2004, granted, now 7,323,365. | ||
| Claims priority of application No. 2003-385418 (JP), filed on Nov. 14, 2003. | ||
| Prior Publication US 2008/0090331 A1, Apr. 17, 2008 | ||
| Int. Cl. H01L 23/495 (2006.01) | ||
| U.S. Cl. 257—668 [29/825] | 3 Claims |

| 1. An apparatus for manufacturing a semiconductor device including a wiring substrate having a first region where a semiconductor
chip is mounted and a second region around the first region, and terminals extending from the first region to the second region
formed on one surface thereof, comprising:
a cutting section that cuts the wiring substrate;
wherein a reinforcing member is provided on another surface of the wiring substrate, the reinforcing member overlapping the
terminals and a part of the reinforcing member protrudes from the first region to the second region; and
wherein the cutting section includes:
a first cutting section cutting the terminals along a boundary between the first region and the second region by punching
through from a surface side having the terminals in the wiring substrate; and
a second cutting section continuously cutting the reinforcing member from an inboard side to an outboard side along the boundary
between the first region and the second region by punching through from a surface side having the reinforcing member in the
wiring substrate.
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