| US 7,582,899 B2 | ||
| Semiconductor device having overlay measurement mark and method of fabricating the same | ||
| Cha-Won Koh, Yongin-si (Korea, Republic of); Sang-Gyun Woo, Yongin-si (Korea, Republic of); Seok-Hwan Oh, Yongin-si (Korea, Republic of); Gi-Sung Yeo, Seoul (Korea, Republic of); Hyun-Jae Kang, Gunpo-si (Korea, Republic of); and Jang-Ho Shin, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Dec. 08, 2005, as Appl. No. 11/296,921. | ||
| Claims priority of application No. 10-2004-0109903 (KR), filed on Dec. 21, 2004. | ||
| Prior Publication US 2006/0131576 A1, Jun. 22, 2006 | ||
| Int. Cl. H01L 23/58 (2006.01); H01L 29/10 (2006.01) | ||
| U.S. Cl. 257—48 [257/E21.318; 257/E21.335; 257/E29.006; 438/462] | 33 Claims |
| 1. A semiconductor device comprising:
a scribe line region disposed on a semiconductor substrate;
a main scale layer having line and space patterns disposed on the scribe line region; and
vernier scale patterns disposed on space regions of the line and space patterns of the main scale layer, the vernier scale
patterns having a line shape and having smaller widths than those of line patterns of the main scale layer, wherein the space
regions of the main scale layer are disposed between the line patterns of the main scale layer.
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