US 7,582,523 B2
Method of manufacturing semiconductor device including insulated-gate field-effect transistors
Tomoya Satonaka, Kanagawa-ken (Japan); and Hideki Oguma, Kanagawa-ken (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jan. 23, 2008, as Appl. No. 12/18,476.
Claims priority of application No. 2007-012699 (JP), filed on Jan. 23, 2007.
Prior Publication US 2008/0176369 A1, Jul. 24, 2008
Int. Cl. H01L 21/00 (2006.01)
U.S. Cl. 438—231  [438/424; 438/585] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device including insulated-gate field-effect transistors, comprising:
forming first and second insulating films on first and second surface regions of a semiconductor substrate respectively;
forming an n-type semiconductor film on the first insulating film and forming a p-type semiconductor film on the second insulating film;
forming a first protective film on the n-type and the p-type semiconductor films;
forming a second protective film of a material on the first protective film, the material being different from that of the first protective film;
removing the second protective film partially to form first and second patterned films respectively above the first and the second surface regions;
introducing impurities into the second patterned film;
oxidizing the first patterned film and the second patterned film containing the introduced impurities to form an oxide film;
etching the oxide film selectively to slim the second patterned film thinner than the first patterned film;
etching the first protective film using the first and the second patterned films as a mask to form third and fourth patterned films, after the slimming;
etching the n-type and the p-type semiconductor films using the third and fourth patterned films as a mask to form first and second gate electrodes, respectively;
implanting n-type impurities into the first surface region using the first gate electrode as a mask and implanting p-type impurities into the second surface region using the second gate electrode as a mask, in order to form source regions and drain regions in the first and the second surface regions respectively.